1. Field of the Invention
The present invention relates to wiring structures for high-current integrated circuits (IC's) equipped with n-phase half bridge circuits, and in particular to a technique for forming wiring in transistor-forming regions.
2. Description of the Prior Art
The recent achievement of miniaturization, cost-saving, high-functionalization and high reliability in the fields of, for instance, FA and OA machinery and tools, has greatly depended on the improvement of various components in size, functions and quality, and further development thereof has been anticipated. For instance, the size of hard disk devices installed in personal computers or the like will certainly be reduced to the 2.5 to 1.8 inch-size within several years. It would be required that the driving and control parts be formed on a single chip and that a driving part capable of processing a current of higher than 1A be developed, for LSI's used in such hard disk devices. Therefore, it is necessary to design an arrangement of transistor-forming regions and wiring structures while taking into consideration the aforementioned circumstances since the ON-state resistance for high-current IC's such as IC's for controlling disk drives is an important factor for defining, for instance, a correlation between the magnitude of the current to be processed and the size thereof.
An example of such a high-current IC which satisfies the requirement is a circuit having a wiring structure as shown in FIG. 1. This circuit shown in FIG. 1 is an IC equipped with a three-phase half bridge circuit for driving and controlling a three-phase motor. FIG. 2 is a circuit diagram of this circuit.
In these figures, there are arranged, in the form of a lattice in the column and row directions, paired transistors, which comprise collective transistors 201 to 203 in first to third phases and collective transistors 204 to 206 in the first to third phases. They are covered with an interlayer insulation film 110. The collective transistors 201 to 203, which are hereafter simply called "transistors" 201 to 203, are arranged on the high side of the circuit, while the collective transistors 204 to 206, which are hereafter simply called "transistors" 204 to 206, are arranged on the low side thereof. FIG. 3 shows the structure of the circuit in cross-section. The transistors are formed by diffusing ions in the surface region of a semiconductor-substrate 100 and the surface thereof is covered with interlayer insulation film 110 as has been discussed above. A plurality of through holes (connecting holes) 110a are formed through interlayer insulation film 110. Top and bottom wiring conductors, as will be explained below, are connected to the corresponding electrode regions of each collective transistor formed on the substrate 110 through the connecting holes 110a in such a way that a source is connected to other sources and a drain is connected to other drains in each collective transistor, and the wiring between the collective transistors is as shown in FIG. 2. Transistors 201 to 203 and transistors 204 to 206 are hereinafter referred to as "high side transistors 201 to 203" and "low side transistors 204 to 206" respectively. A wiring conductor 209, which is depicted with a dot-dash line in FIG. 1, is provided for the first phase output and is arranged in the row direction. Wiring conductor 209 is connected to the source regions of high side transistor 201 and to the drain regions of low side transistor 204 in the first phase. Wiring conductor 209 is provided with a pad 214 for the first phase output at the edge thereof. Wiring conductors 210 and 211, which are also depicted with dot-dash chain lines in FIG. 1, are provided for the second and third phase outputs. Wiring conductors 210 and 211 are respectively connected to the source regions of high side transistors 202 and 203 and to the drain regions of low side transistors 205 and 206 in the second and third phases, and are provided with pads 215 and 216 for the second and third phase outputs at the edges thereof. In addition, a high side common terminal wiring conductor 208, depicted with a double-dot-dash chain line in FIG. 1, extends in the column direction and is conductively connected to the drain regions of high side transistors 201 to 203. Wiring conductor 208 is provided with a pad 212 for the high side common terminal at the edge thereof. A low side common terminal wiring conductor 207 is arranged in the column direction and is conductively connected to the source regions of low side transistors 204 to 206. Wiring conductor 207 is provided with a pad 213 for the low side common terminal at the edge thereof. Each wiring conductor is formed and positioned within the space formed by etching interlayer insulation film 110. Thus, in interlayer insulation film 110, common terminal wiring conductors 207 and 208 constitute the upper side or top wiring layers of a crossed and multilayered wiring structure with respect to wiring conductors 209 to 211 for the first to third outputs. FIG. 4 shows a perspective view of the lower side or bottom wiring conductors 209-211 in the wiring structure. As is shown in FIG. 4, the bottom wiring conductors are formed all over except the vicinity of through holes 110a of interlayer insulation film 110. Therefore, the wiring of the bottom wiring conductors is connected conductively while avoiding the vicinity of through holes 110a. Due to such a structure, the distance needed for each of the first to third phase wiring conductors 209 to 211 and each of the common terminal wiring conductors 207 and 208 can be reduced and the resistance of the wiring conductors can correspondingly be lowered. This accordingly makes it possible to reduce the On-state resistance.
In the foregoing wiring structure, however, bottom wiring conductors 209 to 211 and top wiring conductors 207 and 208 are formed on the surface of the semiconductor substrate in a high density manner and thus occupy a wide surface area thereof. This makes it difficult to form new wiring conductors in the vicinity of the regions for forming the first to third phase high side transistors 201 to 203 and the first to third phase low side transistors 204 to 206, and this greatly limits the degree of freedom for circuit-design of large-scale IC's. The circuit-design is greatly restricted. For instance, the surface area of a semiconductor substrate existing between the elements, i.e., between the first to third phase high side transistors 201 to 203 and first to third phase low side transistors 204 to 206, is covered with wiring conductors 209 to 211 for the first to third phase outputs or the bottom wiring layers and, therefore, isolation contacts cannot be formed on the region existing between these elements. In this case, only one conductive connection which can be selected freely is obtained if one wishes to reverse the source and drain connections with respect to the higher or lower wiring layer.
Moreover, bottom wiring conductors 209 to 211 for the first to third phase outputs and the common terminal wiring conductors (the top wiring conductors) 207 and 208 constitute a crossed and multilayered wiring structure above each transistor-forming region. As shown in FIG. 3, for example, in order to connect the drain of transistor 201 to top wiring conductor 208, the drain should be first connected to the bottom layer, and connected to top wiring conductor 208 via a through hole 110a. In the conventional circuit structure, as described above, when the source of high side transistor 201 is connected to the bottom wiring conductor, the drain next to the source is connected to the top wiring conductor. Therefore, when the source contact area is larger than the drain contact area, since the source of low side transistor 204 must be connected to top wiring conductor 207, the wiring width of the connecting portion of bottom wiring conductor 209 to the drain is reduced, and the wiring resistance of the connecting portion is increased.